1. Technical Field
The present invention relates in general to an improved data processing system and in particular to an improved method and system for performing atomic memory accesses in a processor system. Still more particularly, the present invention relates to an improved method and system for speculatively issuing and executing reservation instructions and partnering conditional store instructions.
2. Description of the Related Art
Designers of modern state-of-the-art data processing systems are continually attempting to enhance performance aspects of such systems. One technique for enhancing data processing efficiency is the achievement of short cycle times and a low Cycles-Per-Instruction (CPI) ratio. In superscalar processor systems, cycle times and CPI ratios are decreased by the simultaneous issuance and execution of multiple instructions. Typically multiple instructions are simultaneously executed through multiple fixed point and floating point instruction execution units which are pipelined in nature. In view of the pipelined nature of processors, in such systems care must be taken to ensure that a result from a particular instruction which is necessary for execution of a subsequent instruction is obtained prior to dispatching the subsequent instruction. In other words, care must be taken to prevent out-of-order execution of particular instructions.
Many techniques have been developed in order to restrict the dispatching of instructions and ensure that "data dependency hazards" due to out-of-order execution do not occur. By one method, the dispatching of a particular instruction is restricted until such time as all preceding instructions in a program order have been dispatched. While this technique ensures that data dependency hazards will not occur, the performance penalty encountered utilizing this technique is substantial.
By another method, the data dependency hazards which occur with simultaneous execution of multiple instructions in each processor cycle have also been addressed by utilizing an approach known as "register renaming." Register renaming is a technique utilized to temporarily place the results of a particular instruction into a register for potential use by later instructions prior to the time the final result from an instruction is placed within a register file. Register renaming is generally accomplished by providing a register file array with extra locations and a pointer arrangement to identify particular physical registers which have been assigned to logical registers. Selected prior art approaches also utilize multiple register file arrays to provide many "read" ports for data or for holding previous results for backup in the case of exceptions.
While register renaming provides the ability to simultaneously dispatch and execute multiple instructions where serial execution might otherwise be necessary, a problem exists with the dispatching of instructions to execution units utilizing such techniques. The requirement that an instruction utilize particular data or operands for execution has generally rendered it impossible to dispatch an instruction and associated data to an execution unit within a single processor cycle, since the dispatch unit, or the execution unit must generally perform a complex read through a lookup table or pointer system to determine which temporary register contains the required data for execution of the instruction.
In order to reduce the cycles needed to dispatch instructions, another method of dispatching instructions has been developed. The method utilizes "serialization" of data which ensures that the execution of these instructions follows rules for maintaining sequential execution of instructions. Intermediate storage buffers are provided for storing the result of an instruction for utilization by other execution units or for future transfer to a general purpose register. By this method, the maintaining of complex lookup tables typically associated with register renaming schemes is not required and thereby instructions may be dispatched within a single processor cycle.
In particular, reservation instructions and partnering conditional store instructions require in-order execution with respect to each other and thereby have been serialized in execution in prior art processor systems. These instructions are often referred to as load and reserve indexed (LARX) instructions and store conditional indexed (STCX) instructions. In particular LARX instructions create a reservation for a particular address for use by a partnered STCX instruction in order to assert an atomic operation. The reservation is checked for validity and the STCX instruction is performed only if the reservation is found valid. The reservation may be lost if other processors or I/O devices reference the address prior to the STCX instruction execution.
In serializing instructions, certain types of instructions may wait many cycles before being issued. In particular, LARX/STCX instructions are often held for multiple cycles before being issued until all instructions upon which the LARX instruction is dependent are executed and complete. In addition, if prior storage references located before the selected LARX instruction according to the program order have not been completed, then the dispatch of any storage references after the LARX instruction are inhibited until the LARX instruction is executed. In some cases, a LARX instruction and those storage references following may wait an undesirable number of cycles before being issued for execution.
From the foregoing, it is apparent that there is a need for a method of issuing LARX instructions such that in-order execution with respect to STCX instructions is maintained, however the instruction does not wait multiple cycles before being issued. Thereby, there is a need to issue and execute LARX instructions in a speculative manner while still maintaining the necessary order of execution with respect to STCX instructions to reduce the number of cycles in which LARX instructions are stalled in issue and execution units.